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(parent: eff0e49) | patch
clk: at91: sama7d65: add clock support
authorRyan Wanner <Ryan.Wanner@microchip.com>
Mon, 7 Jul 2025 11:32:50 +0000 (17:02 +0530)
committerEugen Hristev <eugen.hristev@linaro.org>
Fri, 25 Jul 2025 08:54:43 +0000 (11:54 +0300)
commit8dff5dd290584504569b95b4ea4a69e5c81f5981
treecafcb27670e5c74dd52a792d701633ecec0267adtree
parenteff0e49d1c6c75c92665c285216cf9bd785e5ac1commit | diff
clk: at91: sama7d65: add clock support

Add clock support for SAMA7D65

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
[romain.sioen@microchip.com: add Fractional PLL core
output range]
Signed-off-by: Romain Sioen <romain.sioen@microchip.com>
[varshini.rajendran@microchip.com: adapt driver to upstream]
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
drivers/clk/at91/Makefile diff | blob | blame | history
drivers/clk/at91/sama7d65.c [new file with mode: 0644] blob
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