]> git.ipfire.org Git - thirdparty/kernel/stable.git/commit
can: flexcan: add NXP S32G2/S32G3 SoC support
authorCiprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Mon, 13 Jan 2025 12:07:04 +0000 (14:07 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sun, 20 Apr 2025 08:15:18 +0000 (10:15 +0200)
commit8e7bb6636082a9c64da88aff2af82e2466de060f
tree021b3d5270334a27f79828aebd53f5c07472b6c3
parentfba5f41f1536086e0c24d444865f035ebf300825
can: flexcan: add NXP S32G2/S32G3 SoC support

[ Upstream commit 8503a4b1a24d32e95f3a233062e8f1dc0b2052bd ]

Add device type data for S32G2/S32G3 SoC.

FlexCAN module from S32G2/S32G3 is similar with i.MX SoCs, but interrupt
management is different.

On S32G2/S32G3 SoC, there are separate interrupts for state change, bus
errors, Mailboxes 0-7 and Mailboxes 8-127 respectively.
In order to handle this FlexCAN hardware particularity, first reuse the
'FLEXCAN_QUIRK_NR_IRQ_3' quirk provided by mcf5441x's irq handling
support. Secondly, use the newly introduced
'FLEXCAN_QUIRK_SECONDARY_MB_IRQ' quirk which handles the case where two
separate mailbox ranges are controlled by independent hardware interrupt
lines.

Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Link: https://patch.msgid.link/20250113120704.522307-4-ciprianmarian.costea@oss.nxp.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/net/can/flexcan/flexcan-core.c