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PCI: Cache ACS Capabilities register
authorManivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Fri, 2 Jan 2026 15:34:48 +0000 (21:04 +0530)
committerBjorn Helgaas <bhelgaas@google.com>
Fri, 6 Feb 2026 22:54:12 +0000 (16:54 -0600)
commit8f05a5f6745ccc9ff784736608c5a38edb09acc8
tree4603224c1d525af9c9371470c25244a7bf492845tree
parentc41e2fb67e26b04d919257875fa954aa5f6e392ecommit | diff
PCI: Cache ACS Capabilities register

The ACS Capability register is read-only. Cache it to allow quirks to
override it and to avoid re-reading it.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
[bhelgaas: commit log]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Naresh Kamboju <naresh.kamboju@linaro.org>
Link: https://patch.msgid.link/20260102-pci_acs-v3-2-72280b94d288@oss.qualcomm.com
drivers/pci/pci.c diff | blob | blame | history
include/linux/pci.h diff | blob | blame | history
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