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clk: renesas: r9a09g057: Add clock and reset entries for TSU
authorOvidiu Panait <ovidiu.panait.rb@renesas.com>
Mon, 20 Oct 2025 14:31:05 +0000 (14:31 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 23 Oct 2025 14:31:01 +0000 (16:31 +0200)
commit919bf298dc9fe2cee5abfacb281fb201cda65a44
tree58c23b6e14653c706afc9e8b426777e69310b8f8tree | snapshot
parent934dcccf3ffc7568fdeb363842bb9fc36e1be608commit | diff
clk: renesas: r9a09g057: Add clock and reset entries for TSU

Add module clock and reset entries for the TSU0 and TSU1 blocks on the
Renesas RZ/V2H (R9A09G057) SoC.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251020143107.13974-2-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g057-cpg.c diff | blob | blame | history
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