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clk: renesas: r9a09g047: Add SDHI clocks/resets
authorBiju Das <biju.das.jz@bp.renesas.com>
Sun, 26 Jan 2025 13:46:04 +0000 (13:46 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 3 Feb 2025 10:07:06 +0000 (11:07 +0100)
commit922c892834689939953c74bd34d01788b17feb7e
tree6625eaa7e9d72b1bf18d88b57205a14421fca16ftree
parent90a2bee8a0c2889617d39e637547aa4728fcb43dcommit | diff
clk: renesas: r9a09g047: Add SDHI clocks/resets

Add SDHI[0-2] clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250126134616.37334-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g047-cpg.c diff | blob | blame | history
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git