RISC-V: Generic vec_extract via subreg.

RISC-V: Generic vec_extract via subreg.

We are missing several vec_extract chances because the current autovec
patterns are not comprehensive.  In particular we don't extract from
pseudo-VLA modes that are actually VLS modes (just VLA modes in name).

Rather than add even more mode combinations to vec_extract, this patch
uses a dynamic approach in legitimize_move.  At that point we can just check
if the mode sizes make sense and then emit the same code as before.

This is not the ideal solution as the middle-end and the vectorizer in
particular queries the vec_extract optab for support and won't emit
certain code sequences if it's not present (e.g. in VMAT_STRIDED_SLP
or when trying intermediate-sized vectors in a chain).
For simple BIT_FIELD_REFs it works, though.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_vector_subreg_extract): New
	function that checks for and performs "vector extracts".
	(legitimize_move): Call new function.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/subreg-extract.c: New test.