RISC-V: Optimize VSETVL codegen of SELECT_VL with LEN_MASK_{LOAD, STORE}

RISC-V: Optimize VSETVL codegen of SELECT_VL with LEN_MASK_{LOAD, STORE}

This patch is depending on LEN_MASK_{LOAD,STORE} patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/622742.html

After enabling the LEN_MASK_{LOAD,STORE}, I notice that there is a case that VSETVL PASS need to be optimized:

void
f (int32_t *__restrict a,
   int32_t *__restrict b,
   int32_t *__restrict cond,
   int n)
{
  for (int i = 0; i < 8; i++)
    if (cond[i])
      a[i] = b[i];
}

Before this patch:
f:
        vsetivli        a5,8,e8,mf4,tu,mu   --> Propagate "8" to the following vsetvl
        vsetvli zero,a5,e32,m1,ta,ma
        vle32.v v0,0(a2)
        vsetvli a6,zero,e32,m1,ta,ma
        li      a3,8
        vmsne.vi        v0,v0,0
        vsetvli zero,a5,e32,m1,ta,ma
        vle32.v v1,0(a1),v0.t
        vse32.v v1,0(a0),v0.t
        sub     a4,a3,a5
        beq     a3,a5,.L6
        slli    a5,a5,2
        add     a2,a2,a5
        add     a1,a1,a5
        add     a0,a0,a5
        vsetvli a5,a4,e8,mf4,tu,mu     --> Propagate "a4" to the following vsetvl
        vsetvli zero,a5,e32,m1,ta,ma
        vle32.v v0,0(a2)
        vsetvli a6,zero,e32,m1,ta,ma
        vmsne.vi        v0,v0,0
        vsetvli zero,a5,e32,m1,ta,ma
        vle32.v v1,0(a1),v0.t
        vse32.v v1,0(a0),v0.t
.L6:
        ret

Current VSETLV PASS only enable AVL propagation of VLMAX AVL ("zero").
Now, we enable AVL propagation of immediate && conservative non-VLMAX.

After this patch:

f:
        vsetivli        a5,8,e8,mf4,ta,ma
        vle32.v v0,0(a2)
        vsetvli a6,zero,e32,m1,ta,ma
        li      a3,8
        vmsne.vi        v0,v0,0
        vsetivli        zero,8,e32,m1,ta,ma
        vle32.v v1,0(a1),v0.t
        vse32.v v1,0(a0),v0.t
        sub     a4,a3,a5
        beq     a3,a5,.L6
        slli    a5,a5,2
        vsetvli a4,a4,e8,mf4,ta,ma
        add     a2,a2,a5
        vle32.v v0,0(a2)
        add     a1,a1,a5
        vsetvli a6,zero,e32,m1,ta,ma
        add     a0,a0,a5
        vmsne.vi        v0,v0,0
        vsetvli zero,a4,e32,m1,ta,ma
        vle32.v v1,0(a1),v0.t
        vse32.v v1,0(a0),v0.t
.L6:
        ret

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (vector_insn_info::parse_insn): Ehance
	AVL propagation.
	* config/riscv/riscv-vsetvl.h: New function.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/partial/select_vl-1.c: Add dump checks.
	* gcc.target/riscv/rvv/autovec/partial/select_vl-2.c: New test.