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(parent: 3921c5b) | patch
x86: Only align destination to 1x VEC_SIZE in memset 4x loop
authorNoah Goldstein <goldstein.w.n@gmail.com>
Wed, 1 Nov 2023 20:30:26 +0000 (15:30 -0500)
committerNoah Goldstein <goldstein.w.n@gmail.com>
Tue, 28 Nov 2023 18:06:19 +0000 (12:06 -0600)
commit9469261cf1924d350feeec64d2c80cafbbdcdd4d
tree2d6599f49c3497e64b354a60a6ae4ee644587e05tree
parent3921c5b40f293c57cb326f58713c924b0662ef59commit | diff
x86: Only align destination to 1x VEC_SIZE in memset 4x loop

Current code aligns to 2x VEC_SIZE. Aligning to 2x has no affect on
performance other than potentially resulting in an additional
iteration of the loop.
1x maintains aligned stores (the only reason to align in this case)
and doesn't incur any unnecessary loop iterations.
Reviewed-by: Sunil K Pandey <skpgkp2@gmail.com>
sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S diff | blob | blame | history
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