drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT

drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECT

Starting from Xe3p, there are two different copies of some of the GAM
registers:  the traditional MCR variant at their old locations, and a
new unicast copy known as "main_gamctrl."  The Xe driver doesn't use
these registers directly, but we need to instruct the GuC on which set
it should use.  Since the new, unicast registers are preferred (since
they avoid the need for unnecessary MCR synchronization), set a new GuC
feature flag, GUC_CTL_MAIN_GAMCTRL_QUEUES to convey this decision.  A
new helper function, xe_guc_using_main_gamctrl_queues(), is added for
use in the 3 independent places that need to handle configuration of the
new reporting queues.

The mmio write to enable the main gamctl is only done during the general
GuC upload.  The gamctrl registers are not accessed by the GuC during
hwconfig load.

Last, the ADS blob for communicating the queue addresses contains both a
DPA and GGTT offset. The GuC documentation states that DPA is now MBZ
when using the MAIN_GAMCTRL queues.

Bspec: 76445, 73540
Signed-off-by: Brian Welty <brian.welty@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20251019-xe3p-gamctrl-v1-1-ad66d3c1908f@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>