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(parent: 67ccf6c) | patch
drm/i915/cdclk: Implement Wa_13012396614
authorGustavo Sousa <gustavo.sousa@intel.com>
Mon, 22 Dec 2025 22:18:48 +0000 (19:18 -0300)
committerGustavo Sousa <gustavo.sousa@intel.com>
Mon, 5 Jan 2026 19:44:26 +0000 (16:44 -0300)
commit968290fa8a42d9d2d2fd0fcdeb82d7533e83071d
tree9d182900dd1ce662d0288341475bd9e9e388ab9ftree
parent67ccf6c60bc324d78c24893e8c1eb6a62973838dcommit | diff
drm/i915/cdclk: Implement Wa_13012396614

A new workaround was defined for Xe3_LPD, which requires a tweak on how
we handle MDCLK selection.  Implement it.

Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Link: https://patch.msgid.link/20251222-display-wa-13012396614-timing-of-mdclk-source-selection-v1-2-a2f7e9447f7a@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
drivers/gpu/drm/i915/display/intel_cdclk.c diff | blob | blame | history
drivers/gpu/drm/i915/display/intel_display_wa.c diff | blob | blame | history
drivers/gpu/drm/i915/display/intel_display_wa.h diff | blob | blame | history
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