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Finalise SSSE3 support (counterpart to r1808):
authorJulian Seward <jseward@acm.org>
Sat, 9 Feb 2008 01:16:02 +0000 (01:16 +0000)
committerJulian Seward <jseward@acm.org>
Sat, 9 Feb 2008 01:16:02 +0000 (01:16 +0000)
commit9a38400e7866a0a5c4f6033f7fd3cecac844de81
tree5ca960792a3e4cd84a514ff99c9fdfc035c116e2tree
parent8ddb62873b02fce10061acf4f8540b1cf7c8c5ebcommit | diff
Finalise SSSE3 support (counterpart to r1808):

* support SSSE3 for 32-bit insns

* For 128-bit variants accessing memory, generate an exception
  if effective address is not 128-bit aligned

* Change CPUID output to be Core-2, so now it claims to
  be a Core 2 E6600

git-svn-id: svn://svn.valgrind.org/vex/trunk@1809
VEX/priv/guest-amd64/ghelpers.c diff | blob | blame | history
VEX/priv/guest-amd64/toIR.c diff | blob | blame | history
VEX/priv/guest-x86/ghelpers.c diff | blob | blame | history
VEX/priv/guest-x86/toIR.c diff | blob | blame | history
VEX/priv/host-amd64/hdefs.c diff | blob | blame | history
VEX/priv/host-x86/isel.c diff | blob | blame | history
Mirror of https://sourceware.org/git/valgrind.git