RISC-V: Primary vector pipeline model for sifive 7 series

RISC-V: Primary vector pipeline model for sifive 7 series

This commit introduces a primary vector pipeline model for the SiFive 7
series, that pipeline model is kind of simplified version, it only
defined vector command queue, arithmetic unit, and vector load store
unit.

The latency of real hardware is LMUL-aware, but I realize that will
complicate the model a lots, so I just use a simplified version, which
all LMUL use same latency, we may improve it later once we have found
meaningful performance difference.

gcc/ChangeLog:

	* config/riscv/sifive-7.md: Add primary vector pipeline model
	for SiFive 7 series.