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dt-bindings: iio: adc: Add the NXP SAR ADC for s32g2/3 platforms
authorDaniel Lezcano <daniel.lezcano@linaro.org>
Mon, 8 Dec 2025 02:08:18 +0000 (03:08 +0100)
committerJonathan Cameron <Jonathan.Cameron@huawei.com>
Sun, 21 Dec 2025 11:41:12 +0000 (11:41 +0000)
commita19489ca82bb5cedfe348326905fb66d66ffac65
tree0b93600ead6627ddbfdc78ae3f7107470fd3956dtree
parent048a15b7211ada26d170b5a61248fb3356739976commit | diff
dt-bindings: iio: adc: Add the NXP SAR ADC for s32g2/3 platforms

The s32g2 and s32g3 NXP platforms have two instances of a Successive
Approximation Register ADC. It supports the raw, trigger and scan
modes which involves the DMA. Add their descriptions.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Documentation/devicetree/bindings/iio/adc/nxp,s32g2-sar-adc.yaml [new file with mode: 0644] blob
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