RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT

RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT

This incorrect codes blocks the scalable RVV auto-vectorization.
Take a look at this target hook implementation of aarch64.
They only have the similiar handling on TARGET_SIMD.

They let movmisalign<mode> to handle scalable vector of SVE.
For RVV, we should follow the same implementation of ARM SVE.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_support_vector_misalignment): Fix
	incorrect codes.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/v-2.c: Adapt testcase.
	* gcc.target/riscv/rvv/autovec/zve32f-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32f-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve32x-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64d-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64d-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64d_zvl128b-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64f-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64f-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64f_zvl128b-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64x-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64x-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/zve64x_zvl128b-2.c: Ditto.