RISC-V: Fix wrong check of register occurrences [PR109535]

RISC-V: Fix wrong check of register occurrences [PR109535]

count_occurrences will conly count same RTX (same code and same mode),
but what we want to track is the occurrence of a register, a register
might appeared in the insn with different mode or contain in SUBREG.

Testcase coming from Kito.

gcc/ChangeLog:

	PR target/109535
	* config/riscv/riscv-vsetvl.cc (count_regno_occurrences): New function.
	(pass_vsetvl::cleanup_insns): Fix bug.

gcc/testsuite/ChangeLog:

	PR target/109535
	* g++.target/riscv/rvv/base/pr109535.C: New test.
	* gcc.target/riscv/rvv/base/pr109535.c: New test.

Signed-off-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Co-authored-by: kito-cheng <kito.cheng@sifive.com>