RISC-V: Support Sstvecd extension.

RISC-V: Support Sstvecd extension.

Support the Sstvecd extension, which allows Supervisor Trap Vector
Base Address register (stvec) to support Direct mode.

gcc/ChangeLog:

	* config/riscv/riscv-ext.def: New extension definition.
	* config/riscv/riscv-ext.opt: New extension mask.
	* doc/riscv-ext.texi: Document the new extension.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-sstvecd.c: New test.

Signed-off-by: Jiawei <jiawei@iscas.ac.cn>