RISC-V Adjust long unconditional branch sequence

RISC-V Adjust long unconditional branch sequence

Andrew and I independently noted the long unconditional branch sequence was
using the "call" pseudo op.  Technically it works, but it's a bit odd.  This
patch flips it to use the "jump" pseudo-op.

This was tested with a hacked-up local compiler which forced all branches/jumps
to be long jumps.  Naturally it triggered some failures for scan-asm tests but
no execution regressions (which is mostly what I was testing for).

I've updated the long branch support item in the RISE wiki to indicate that we
eventually want a register scavenging approach with a fallback to $ra in the
future so that we don't muck up the return address predictors.  It's not
super-high priority and shouldn't be terrible to implement given we've got the
$ra fallback when a suitable register can not be found.

gcc/
	* config/riscv/riscv.md (jump): Adjust sequence to use a "jump"
	pseudo op instead of a "call" pseudo op.