[PATCH v2 2/3] RISC-V: setmem for RISCV with V extension

[PATCH v2 2/3] RISC-V: setmem for RISCV with V extension

This is primarily Sergei's work, my contributions were limited to
merging his expander with the one that's on the trunk, allowing
non-constant value and trivial testsuite adjustments due to option renaming.

I'm doing setmem first because it's the easiest.  The others will follow
soon enough.

I've tested this in my system, waiting on pre-commit CI to render its
verdict before moving forward.

gcc/ChangeLog

	* config/riscv/riscv-protos.h (riscv_vector::expand_vec_setmem): New
	function declaration.

	* config/riscv/riscv-string.cc (riscv_vector::expand_vec_setmem): New
	function: this generates an inline vectorised memory set, if and only if
	we know the entire operation can be performed in a single vector store.

	* config/riscv/riscv.md (setmem<mode>): Try riscv_vector::expand_vec_setmem
	for constant lengths.  Do not require operand 2 to be a constant.

gcc/testsuite/ChangeLog

	* gcc.target/riscv/rvv/base/setmem-1.c: New tests
	* gcc.target/riscv/rvv/base/setmem-2.c: New tests
	* gcc.target/riscv/rvv/base/setmem-3.c: New tests