RISC-V: Implement -m{,no}fence-tso

RISC-V: Implement -m{,no}fence-tso

Some processors from T-Head don't implement the `fence.tso` instruction
natively and instead trap to firmware.  This breaks some users who
haven't yet updated the firmware and one could imagine it breaking users
who are trying to build firmware if they're using the C memory model.

So just add an option to disable emitting it, in a similar fashion to
how we allow users to forbid other instructions.

Link: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1070959
---
I've just smoke tested this one, but

    void func(void) { __atomic_thread_fence(__ATOMIC_ACQ_REL); }

generates `fence.tso` without the argument and `fence rw,rw` with
`-mno-fence-tso`, so it seems to be at least mostly there.  I figured
I'd just send it up for comments before putting together the DG bits:
it's kind of a pain to carry around these workarounds for unimplemented
instructions, but it's in HW so there's not much we can do about that.

gcc/ChangeLog:

	* config/riscv/riscv.opt: Add -mno-fence-tso.
	* config/riscv/sync-rvwmo.md (mem_thread_fence_rvwmo): Respect
	-mno-fence-tso.
	* doc/invoke.texi (RISC-V): Document -mno-fence-tso.