]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commit
RISC-V: add Smrnmi 1.0 instruction support
authorJerry Zhang Jian <jerry.zhangjian@sifive.com>
Mon, 24 Mar 2025 14:10:11 +0000 (22:10 +0800)
committerNelson Chu <nelson@rivosinc.com>
Wed, 26 Mar 2025 02:16:05 +0000 (10:16 +0800)
commita7ecc1ba9715ac8f3a7772b9d7155f4c00ae2daf
treec0fc70b70b5e76b154d0e6839f0f9460aa91c32f
parente5db6129d8d51befe492434d3ebea065cab9adcb
RISC-V: add Smrnmi 1.0 instruction support

Add instruction `mnret' support

Ref:
https://github.com/riscv/riscv-isa-manual/blob/bb8b9127f81965eeff2d150c211d1c89376591c4/src/rnmi.adoc
https://github.com/riscv/riscv-opcodes/blob/946eb673874b3a0f2474d1424dc28bc7ee53c306/extensions/rv_smrnmi

bfd/ChangeLog:
    * elfxx-riscv.c: Add new Smrnmi instruction class handling

gas/ChangeLog:
    * testsuite/gas/riscv/smrnmi.s: New test for mnret
    * testsuite/gas/riscv/rmrnmi.d: Likewise

include/ChangeLog:
    * opcode/ricsv-opc.h: Add MATCH_MNRET, MASK_MNRET
    * opcode/riscv.h: Add new instruction class

opcodes/ChangeLog:
    * riscv-opc.c: Add `mnret' instruction

Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
bfd/elfxx-riscv.c
gas/testsuite/gas/riscv/smrnmi.d [new file with mode: 0644]
gas/testsuite/gas/riscv/smrnmi.s [new file with mode: 0644]
include/opcode/riscv-opc.h
include/opcode/riscv.h
opcodes/riscv-opc.c