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xtensa: xtfpga: fix serial port register width and endianness
authorMax Filippov <jcmvbkbc@gmail.com>
Mon, 24 Aug 2015 16:44:46 +0000 (19:44 +0300)
committerChris Zankel <chris@zankel.net>
Fri, 11 Mar 2016 08:53:31 +0000 (08:53 +0000)
commitabfbd89595e91d5108f807e10bbd2152bc55f36b
treefea9190c224b121a092723b450f3d03a9b84a992tree | snapshot
parent4611bf7eb52599cb7549eed10f1ab609cbcdfa4bcommit | diff
xtensa: xtfpga: fix serial port register width and endianness

Serial port is attached to XTFPGA boards as native endian device, mark
it as such in DTS and pass correct endianness in platform data.
Set register width in DTS to 4, this way it matches the platform data
and works correctly on big-endian CPUs.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
arch/xtensa/boot/dts/xtfpga.dtsi diff | blob | blame | history
arch/xtensa/platforms/xtfpga/setup.c diff | blob | blame | history
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