]> git.ipfire.org Git - thirdparty/gcc.git/commit
LoongArch: Allow moving TImode vectors
authorXi Ruoyao <xry111@xry111.site>
Fri, 24 Jan 2025 00:33:39 +0000 (08:33 +0800)
committerXi Ruoyao <xry111@xry111.site>
Wed, 19 Feb 2025 06:34:44 +0000 (14:34 +0800)
commitac1b0586297c6d4d39380f77a4915728511d79f0
tree2ab65c8a77cac89bbb9b6a1ec0167866c06f0b06
parented9794546db62279199a1cd84b8cdacd14ceab42
LoongArch: Allow moving TImode vectors

We have some vector instructions for operations on 128-bit integer, i.e.
TImode, vectors.  Previously they had been modeled with unspecs, but
it's more natural to just model them with TImode vector RTL expressions.

For the preparation, allow moving V1TImode and V2TImode vectors in LSX
and LASX registers so we won't get a reload failure when we start to
save TImode vectors in these registers.

This implicitly depends on the vrepli optimization: without it we'd try
"vrepli.q" which does not really exist and trigger an ICE.

gcc/ChangeLog:

* config/loongarch/lsx.md (mov<LSX:mode>): Remove.
(movmisalign<LSX:mode>): Remove.
(mov<LSX:mode>_lsx): Remove.
* config/loongarch/lasx.md (mov<LASX:mode>): Remove.
(movmisalign<LASX:mode>): Remove.
(mov<LASX:mode>_lasx): Remove.
* config/loongarch/loongarch-modes.def (V1TI): Add.
(V2TI): Mention in the comment.
* config/loongarch/loongarch.md (mode): Add V1TI and V2TI.
* config/loongarch/simd.md (ALLVEC_TI): New mode iterator.
(mov<ALLVEC_TI:mode): New define_expand.
(movmisalign<ALLVEC_TI:mode>): Likewise.
(mov<ALLVEC_TI:mode>_simd): New define_insn_and_split.
gcc/config/loongarch/lasx.md
gcc/config/loongarch/loongarch-modes.def
gcc/config/loongarch/loongarch.md
gcc/config/loongarch/lsx.md
gcc/config/loongarch/simd.md