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(parent: 9d462f5) | patch
riscv: defconfig: enable Andes SoC
authorBen Zong-You Xie <ben717@andestech.com>
Fri, 11 Jul 2025 13:30:24 +0000 (21:30 +0800)
committerArnd Bergmann <arnd@arndb.de>
Mon, 21 Jul 2025 14:51:52 +0000 (16:51 +0200)
commitad087c91eb87bebd79f05a4c9b5cfbe72d6186fa
tree167c282097661ae4d4ee1612441a343651203b1etree
parent9d462f56db7a0fdb0c814b34a6f9bdd01ebc23f5commit | diff
riscv: defconfig: enable Andes SoC

Enable Andes SoC config in defconfig to allow the default
upstream kernel to boot on Voyager board.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-9-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arch/riscv/configs/defconfig diff | blob | blame | history
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