nvptx: Add (experimental) support for HFmode with -misa=sm_53

nvptx: Add (experimental) support for HFmode with -misa=sm_53

The recent flurry of activity around HFmode on gcc-patches intrigued me
to investigate adding HFmode support to the nvptx backend.  NVidia GPUs
with an SM ISA above 5.3 support IEEE 16-bit floating point instructions.
Hence, this patch adds support for -misa=sm_53, and implements some
backend patterns/insns sufficient for a proof-of-concept prototype.

The following has been tested on nvptx-none, hosted on x86_64-pc-linux-gnu
with a "make" and "make -k check" with no new failures.

gcc/ChangeLog:

	* config/nvptx/nvptx-opts.h (ptx_isa): Add PTX_ISA_SM53 ISA level
	to enumeration.
	* config/nvptx/nvptx.opt: Add sm_53 to -misa.
	* config/nvptx/nvptx-modes.def: Add support for HFmode.
	* config/nvptx/nvptx.h (TARGET_SM53):
	New helper macro to conditionalize functionality on target ISA.
	* config/nvptx/nvptx-c.c (nvptx_cpu_cpp_builtins): Add __PTX_SM__
	support for the new ISA levels.
	* config/nvptx/nvptx.c (nvtx_ptx_type_from_mode): Support new HFmode
	with the ".f16" suffix/qualifier.
	(nvptx_file_start): Add support for TARGET_SM53.
	(nvptx_omp_device_kind_arch_isa): Add support for TARGET_SM53
	and tweak TARGET_SM35.
	(nvptx_scalar_mode_supported_p): Target hook with conditional
	HFmode support on TARGET_SM53 and higher.
	(nvptx_libgcc_floating_mode_supported_p): Likewise.
	(TARGET_SCALAR_MODE_SUPPORTED_P): Use nvptx_scalar_mode_supported_p.
	(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Likewise, use new hook.
	* config/nvptx/nvptx.md (*movhf_insn): New define_insn.
	(movhf): New define_expand for HFmode moves.
	(addhf3, subhf3, mulhf, extendhf<mode>2, trunc<mode>hf2): New
	instructions conditional on TARGET_SM53 (i.e. -misa=sm_53).

gcc/testsuite/ChangeLog:

	* gcc.target/nvptx/float16-1.c: New test case.