ARC: Improve DImode left shift by a single bit.

ARC: Improve DImode left shift by a single bit.

This patch improves the code generated for x << 1 (and for x + x) when
X is 64-bit DImode, using the same two instruction code sequence used
for DImode addition.

For the test case:

long long foo(long long x) { return x << 1; }

GCC -O2 currently generates the following code:

foo:    lsr     r2,r0,31
        asl_s   r1,r1,1
        asl_s   r0,r0,1
        j_s.d   [blink]
        or_s    r1,r1,r2

and on CPU without a barrel shifter, i.e. -mcpu=em

foo:	add.f   0,r0,r0
        asl_s   r1,r1
        rlc     r2,0
        asl_s   r0,r0
        j_s.d   [blink]
        or_s    r1,r1,r2

with this patch (both with and without a barrel shifter):

foo:	add.f   r0,r0,r0
        j_s.d   [blink]
        adc     r1,r1,r1

A similar optimization is also applicable to H8300H, that could also use
a two instruction sequence (plus rts) but currently GCC generates 16
instructions (plus an rts) for foo above.

2023-11-03  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
	* config/arc/arc.md (addsi3): Fix GNU-style code formatting.
	(adddi3): Change define_expand to generate a *adddi3.
	(*adddi3): New define_insn_and_split to lower DImode additions
	during the split1 pass (after combine and before reload).
	(ashldi3): New define_expand to (only) generate *ashldi3_cnt1
	for DImode left shifts by a single bit.
	(*ashldi3_cnt1): New define_insn_and_split to lower DImode
	left shifts by one bit to an *adddi3.

gcc/testsuite/ChangeLog
	* gcc.target/arc/adddi3-1.c: New test case.
	* gcc.target/arc/ashldi3-1.c: Likewise.