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PowerPC: llrint/llrintf POWER8 optimization
authorAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Tue, 18 Feb 2014 14:29:29 +0000 (09:29 -0500)
committerAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Mon, 3 Mar 2014 16:46:13 +0000 (10:46 -0600)
commitb34f8e9fcd1274e69a9a59a28c270e2cada39c95
treeb0d41125a929adddc845507eeb297bdd3c78e564tree
parentc3241bcd73c47d2bcd2a5ffe84a21d4853c8c938commit | diff
PowerPC: llrint/llrintf POWER8 optimization

This patch add a optimized llrint/llrintf implementation for POWER8
using the new Move From VSR Doubleword instruction to gains some
cycles from FP to GRP register move.

Backport of 1ad8950a3ea4056ed343d681b5146f4b4aa27e10
ChangeLog diff | blob | blame | history
sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile diff | blob | blame | history
sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint-power8.S [new file with mode: 0644] blob
sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint.c diff | blob | blame | history
sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S [new file with mode: 0644] blob
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