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(parent: 60e9f77) | patch
drm/msm/registers: Sync GPU registers from mesa
authorRob Clark <robin.clark@oss.qualcomm.com>
Mon, 8 Sep 2025 19:30:08 +0000 (12:30 -0700)
committerRob Clark <robin.clark@oss.qualcomm.com>
Wed, 10 Sep 2025 21:48:12 +0000 (14:48 -0700)
commitb5bad77e1e3c7249e4c0c88f98477e1ee7669b63
treeaefee623625cfb656fd01f148280b11b53c82530tree | snapshot
parent60e9f776b7932d67c88e8475df7830cb9cdf3154commit | diff
drm/msm/registers: Sync GPU registers from mesa

In particular, to pull in a SP_READ_SEL_LOCATION bitfield size fix to
fix a7xx GPU snapshot.

Sync from mesa commit 15ee3873aa4d ("freedreno/registers: Update GMU
register xml").

Cc: Karmjit Mahil <karmjit.mahil@igalia.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673558/
drivers/gpu/drm/msm/adreno/a6xx_gpu.c diff | blob | blame | history
drivers/gpu/drm/msm/adreno/a6xx_preempt.c diff | blob | blame | history
drivers/gpu/drm/msm/registers/adreno/a6xx.xml diff | blob | blame | history
drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml diff | blob | blame | history
drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml diff | blob | blame | history
drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml diff | blob | blame | history
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