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intc/riscv_aplic: Fix target register read when source is inactive
authorYang Jialong <z_bajeer@yeah.net>
Mon, 28 Jul 2025 05:51:14 +0000 (13:51 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 30 Jul 2025 00:59:26 +0000 (10:59 +1000)
commitb6f1244678bebaf7e2c775cfc66d452f95678ebf
tree0a028777bcaed9d5a448aa4787cab1d75e739bb2tree
parentf3c8b7767f2e1fac37c727ca17b69e4f1e3351f2commit | diff
intc/riscv_aplic: Fix target register read when source is inactive

The RISC-V Advanced interrupt Architecture:
4.5.16. Interrupt targets:
If interrupt source i is inactive in this domain, register target[i] is
read-only zero.

Signed-off-by: Yang Jialong <z_bajeer@yeah.net>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250728055114.252024-1-z_bajeer@yeah.net>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/intc/riscv_aplic.c diff | blob | blame | history
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