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ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode
authorRicky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Tue, 24 Sep 2024 09:44:29 +0000 (17:44 +0800)
committerAndrew Jeffery <andrew@codeconstruct.com.au>
Fri, 13 Dec 2024 05:16:58 +0000 (15:46 +1030)
commitb7b71409c9b9ec4607563e87f695bfccd7e7e350
treea0a766fc5d5ce76b731bd659d528ab735720fe65tree | snapshot
parent7161ec8386a682b1c0be824e3684537c1dd997f3commit | diff
ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode

Revise quad mode to dual mode to keep the write protect feature for the
SPI flash because the WP pin is the same pin with IO2 pin in quad mode.

Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20240924094430.272074-2-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts diff | blob | blame | history
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