]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Add xfail test case for highpart overlap floating-point widen insn
authorPan Li <pan2.li@intel.com>
Mon, 22 Apr 2024 08:07:36 +0000 (16:07 +0800)
committerPan Li <pan2.li@intel.com>
Mon, 22 Apr 2024 08:30:38 +0000 (16:30 +0800)
commitb991193eb8a79ec7562f3de3df866df9f041015a
treeb5d5da31295d4509640016f6796851c6b827b018
parent4df96b4ec788f2d588febf3555685f2700b932b3
RISC-V: Add xfail test case for highpart overlap floating-point widen insn

We reverted below patch for register group overlap, add the related
insn test and mark it as xfail.  And we will remove the xfail
after we support the register overlap in GCC-15.

8614cbb2534 RISC-V: Support highpart overlap for floating-point widen instructions

The below test suites are passed.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pr112431-10.c: New test.
* gcc.target/riscv/rvv/base/pr112431-11.c: New test.
* gcc.target/riscv/rvv/base/pr112431-12.c: New test.
* gcc.target/riscv/rvv/base/pr112431-13.c: New test.
* gcc.target/riscv/rvv/base/pr112431-14.c: New test.
* gcc.target/riscv/rvv/base/pr112431-15.c: New test.
* gcc.target/riscv/rvv/base/pr112431-7.c: New test.
* gcc.target/riscv/rvv/base/pr112431-8.c: New test.
* gcc.target/riscv/rvv/base/pr112431-9.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-10.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-11.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-12.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-13.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-14.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-15.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-7.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-8.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-9.c [new file with mode: 0644]