]> git.ipfire.org Git - thirdparty/kernel/stable.git/commit
riscv: dts: starfive: add assigned-clock* to limit frquency
authorWilliam Qiu <william.qiu@starfivetech.com>
Fri, 22 Sep 2023 06:28:34 +0000 (14:28 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 18 Sep 2024 17:24:10 +0000 (19:24 +0200)
commitbd9c3c2d7e44ee896e6248d3acffe8d0f43b27c2
tree34fcdfdfcae4582249bfdab0c355c3075f678095
parente43364f578cdc2f8083abbc0cb743ea55e827c29
riscv: dts: starfive: add assigned-clock* to limit frquency

commit af571133f7ae028ec9b5fdab78f483af13bf28d3 upstream.

In JH7110 SoC, we need to go by-pass mode, so we need add the
assigned-clock* properties to limit clock frquency.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: WangYuli <wangyuli@uniontech.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi