RISC-V: Support RVV VREINTERPRET from vbool*_t to vuint*m1_t

RISC-V: Support RVV VREINTERPRET from vbool*_t to vuint*m1_t

This patch support the RVV VREINTERPRET from the vbool*_t to the
vuint*m1_t.  Aka:

vuint*m1_t __riscv_vreinterpret_x_x(vbool*_t);

These APIs help the users to convert vector the vbool*_t to the LMUL=1
unsigned integer vint*_t.  According to the RVV intrinsic SPEC as below,
the reinterpret intrinsics only change the types of the underlying contents.

https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#reinterpret-vbool-o-vintm1

For example, given below code.
vuint8m1_t test_vreinterpret_v_b1_vuint8m1 (vbool1_t src) {
  return __riscv_vreinterpret_v_b1_u8m1 (src);
}

It will generate the assembly code similar as below:
vsetvli a5,zero,e8,m8,ta,ma
vlm.v   v1,0(a1)
vs1r.v  v1,0(a0)
ret

Please NOTE the test files doesn't cover all the possible combinations
of the intrinsic APIs introduced by this PATCH due to too many.
This is the last PATCH for the reinterpret between the signed/unsigned
and the bool vector types.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

	* config/riscv/genrvv-type-indexer.cc (main): Add
	unsigned_eew*_lmul1_interpret for indexer.
	* config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
	Register vuint*m1_t interpret function.
	* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
	New macro for vuint8m1_t.
	(DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
	(DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
	(DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
	(vbool1_t): Add to unsigned_eew*_interpret_ops.
	(vbool2_t): Likewise.
	(vbool4_t): Likewise.
	(vbool8_t): Likewise.
	(vbool16_t): Likewise.
	(vbool32_t): Likewise.
	(vbool64_t): Likewise.
	* config/riscv/riscv-vector-builtins.cc (DEF_RVV_UNSIGNED_EEW8_LMUL1_INTERPRET_OPS):
	New macro for vuint*m1_t.
	(DEF_RVV_UNSIGNED_EEW16_LMUL1_INTERPRET_OPS): Likewise.
	(DEF_RVV_UNSIGNED_EEW32_LMUL1_INTERPRET_OPS): Likewise.
	(DEF_RVV_UNSIGNED_EEW64_LMUL1_INTERPRET_OPS): Likewise.
	(required_extensions_p): Add vuint*m1_t interpret case.
	* config/riscv/riscv-vector-builtins.def (unsigned_eew8_lmul1_interpret):
	Add vuint*m1_t interpret to base type.
	(unsigned_eew16_lmul1_interpret): Likewise.
	(unsigned_eew32_lmul1_interpret): Likewise.
	(unsigned_eew64_lmul1_interpret): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c:
	Enrich test cases.