RISC-V: Fix incorrect optimization options passing to strided ld/st test

RISC-V: Fix incorrect optimization options passing to strided ld/st test

The testcases of vector strided load/store are designed to pick up
different sorts of optimization options but actually these option
are ignored according to the Execution log of gcc.log.  This patch
would like to make it correct, and then you will see the build option
similar as below from the gcc.log.

Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m1 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m1 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m4 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m8 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=dynamic ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m8 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m4 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=m2 ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=scalable -mrvv-max-lmul=dynamic ...
Executing ... strided_ld_st-1-f16.c -O3 -mrvv-vector-bits=zvl -mrvv-max-lmul=m2 ...

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization options.

Signed-off-by: Pan Li <pan2.li@intel.com>