RISC-V: Support integer mult highpart auto-vectorization

RISC-V: Support integer mult highpart auto-vectorization

This patch is adding an obvious missing mult_high auto-vectorization pattern.

Consider this following case:
void __attribute__ ((noipa))			\
mod_##TYPE (TYPE *__restrict dst, TYPE *__restrict src, int count)	\
{						\
  for (int i = 0; i < count; ++i)		\
    dst[i] = src[i] / 17;			\
}

  T (int32_t) \

TEST_ALL (DEF_LOOP)

Before this patch:
mod_int32_t:
        ble     a2,zero,.L5
        li      a5,17
        vsetvli a3,zero,e32,m1,ta,ma
        vmv.v.x v2,a5
.L3:
        vsetvli a5,a2,e8,mf4,ta,ma
        vle32.v v1,0(a1)
        vsetvli a3,zero,e32,m1,ta,ma
        slli    a4,a5,2
        vdiv.vv v1,v1,v2
        sub     a2,a2,a5
        vsetvli zero,a5,e32,m1,ta,ma
        vse32.v v1,0(a0)
        add     a1,a1,a4
        add     a0,a0,a4
        bne     a2,zero,.L3
.L5:
        ret

After this patch:
mod_int32_t:
	ble	a2,zero,.L5
	li	a5,2021163008
	addiw	a5,a5,-1927
	vsetvli	a3,zero,e32,m1,ta,ma
	vmv.v.x	v3,a5
.L3:
	vsetvli	a5,a2,e8,mf4,ta,ma
	vle32.v	v2,0(a1)
	vsetvli	a3,zero,e32,m1,ta,ma
	slli	a4,a5,2
	vmulh.vv	v1,v2,v3
	sub	a2,a2,a5
	vsra.vi	v2,v2,31
	vsra.vi	v1,v1,3
	vsub.vv	v1,v1,v2
	vsetvli	zero,a5,e32,m1,ta,ma
	vse32.v	v1,0(a0)
	add	a1,a1,a4
	add	a0,a0,a4
	bne	a2,zero,.L3
.L5:
	ret

Even though a single "vdiv" is lower into "1 vmulh + 2 vsra + 1 vsub",
4 more instructions are generated, we belive it's much better than before
since division is very slow in the hardward.

gcc/ChangeLog:

	* config/riscv/autovec.md (smul<mode>3_highpart): New pattern.
	(umul<mode>3_highpart): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/mulh-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/mulh-2.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/mulh_run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/mulh_run-2.c: New test.