]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Add xfail test case for widening register overlap of vf4/vf8
authorPan Li <pan2.li@intel.com>
Mon, 22 Apr 2024 02:11:25 +0000 (10:11 +0800)
committerPan Li <pan2.li@intel.com>
Mon, 22 Apr 2024 06:08:58 +0000 (14:08 +0800)
commitc4fdbdac1226787b4d33046f0be189a24dac468e
treee1e82bc20433731f9d6bf3dca24e8ea6c244fc03
parentec78916bb37bec0cd3ede5c6263387345ce16f94
RISC-V: Add xfail test case for widening register overlap of vf4/vf8

We reverted below patch for register group overlap, add the related
insn test and mark it as xfail.  And we will remove the xfail
after we support the register overlap in GCC-15.

303195e2a6b RISC-V: Support widening register overlap for vf4/vf8

The below test suites are passed.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/pr112431-16.c: New test.
* gcc.target/riscv/rvv/base/pr112431-17.c: New test.
* gcc.target/riscv/rvv/base/pr112431-18.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-16.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-17.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-18.c [new file with mode: 0644]