[PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32

[PATCH][RISC-V][PR target/70557] Improve storing 0 to memory on rv32

Patch is originally from Siarhei Volkau <lis8215@gmail.com>.

RISC-V has a zero register (x0) which we can use to store zero into memory
without loading the constant into a distinct register. Adjust the constraints
of the 32-bit movdi_32bit pattern to recognize that we can store 0.0 into
memory using x0 as the source register.

This patch only affects RISC-V. It has been regression tested on riscv64-elf.
Jeff has also tested this in his tester (riscv64-elf and riscv32-elf) with no
regressions.

	PR target/70557
gcc/
	* config/riscv/riscv.md (movdi_32bit): Add "J" constraint to allow storing 0
	directly to memory.