]> git.ipfire.org Git - thirdparty/gcc.git/commit
x86: Move AESNI generation to Skylake and Goldmont
authorhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 30 Aug 2018 15:59:41 +0000 (15:59 +0000)
committerhjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
Thu, 30 Aug 2018 15:59:41 +0000 (15:59 +0000)
commitc9d25f8c66b8cfb996e07b6919f6a235ada9f65a
treeaf0016db3b0f6c5a9e73b142d8373fffc9bc9760
parent995068e42e1f2296ad1d5fc89852e50a43dbe211
x86: Move AESNI generation to Skylake and Goldmont

The instruction set first appeared with Westmere, but not all processors
in that and the next few generations have the instructions. According to
Wikipedia[1], the first generation in which all SKUs have AES
instructions are Skylake and Goldmont. I can't find any Skylake,
Kabylake, Kabylake-R or Cannon Lake currently listed at
https://ark.intel.com that says "IntelĀ® AES New Instructions" "No".

[1] https://en.wikipedia.org/wiki/AES_instruction_set

2018-08-30  Thiago Macieira  <thiago.macieira@intel.com>

* config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES.
(PTA_SKYLAKE): Add PTA_AES.
(PTA_GOLDMONT): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@263989 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog
gcc/config/i386/i386.c