[Morello] All remaining load and store instructions

[Morello] All remaining load and store instructions

- LDR/STR immediate, indexed and register offset
- LDUR/STUR
- LDTR/STTR

gas/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* config/tc-aarch64.c (parse_operands, fix_insn): Add
	A64C_ADDR_SIMM9.
	(try_to_encode_as_unscaled_ldst): Add capability loads.
	* testsuite/gas/aarch64/morello_ldst-c64.d: Add tests.
	* testsuite/gas/aarch64/morello_ldst.d: Likewise.
	* testsuite/gas/aarch64/morello_ldst.s: Likewise.

include/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* opcode/aarch64.h (aarch64_opnd): Add A64C_ADDR_SIMM9.
	(aarch64_op): Add OP_STR_POS_2, OP_LDR_POS_2, OP_LDUR_2,
	OP_STUR_2.

opcodes/ChangeLog:

2020-10-20  Siddhesh Poyarekar  <siddesh.poyarekar@arm.com>

	* aarch64-asm.c (aarch64_ins_addr_simm): Support scaling.
	* aarch64-dis.c (aarch64_ext_addr_simm): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p,
	aarch64_print_operand): Add A64C_ADDR_SIMM9.
	* aarch64-tbl.h (aarch64_opcode_table): New instructions.
	(AARCH64_OPERANDS): New operands.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.