Introduce simple peephole2 optimization which substitutes a sequence of
four consecutive load or store (LDR, STR) instructions with two load or
store pair (LDP, STP) instructions for 2 element supported vector modes
(V2SI, V2SF, V2DI, and V2DF).
Generated load / store pair instruction offset is adjusted accordingly.
Bootstrapped and tested on aarch64-none-linux-gnu.
* config/aarch64/aarch64-ldpstp.md: Add two peepholes for adjusted vector
V2SI, V2SF, V2DI, V2DF load pair and store pair modes.
* config/aarch64/aarch64-protos.h (aarch64_gen_adjusted_ldpstp):
Change mode parameter to machine_mode.
(aarch64_operands_adjust_ok_for_ldpstp): Change mode parameter to
machine_mode.
* config/aarch64/aarch64.c (aarch64_operands_adjust_ok_for_ldpstp):
Change mode parameter to machine_mode.
(aarch64_gen_adjusted_ldpstp): Change mode parameter to machine_mode.
* config/aarch64/iterators.md (VP_2E): New iterator for 2 element vectors.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/ldp_vec_v2sf.c: New test.
* gcc.target/aarch64/ldp_vec_v2si.c: New test.
* gcc.target/aarch64/stp_vec_v2df.c: New test.
* gcc.target/aarch64/stp_vec_v2di.c: New test.
* gcc.target/aarch64/stp_vec_v2sf.c: New test.
* gcc.target/aarch64/stp_vec_v2si.c: New test.