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RISC-V: Fix the the operand alignment for strided load/store pattern [NFC]
authorPan Li <pan2.li@intel.com>
Fri, 20 Dec 2024 06:44:10 +0000 (14:44 +0800)
committerPan Li <pan2.li@intel.com>
Sun, 22 Dec 2024 02:36:46 +0000 (10:36 +0800)
commitcf59bf844037ae952f5058d0fd49e1f4f0cf907e
tree8249a015e1eb1a9490a6b1c5ea7d0b4c7960ad55tree
parentae3e783e23a30e9856e1504c5542acbcb0050e67commit | diff
RISC-V: Fix the the operand alignment for strided load/store pattern [NFC]

Just notice the unalignment operand for strided load/store pattern when
bugfix the strided load/store memory alias, would like to make it align.

gcc/ChangeLog:

* config/riscv/autovec.md: Align the operand for strided
load/store pattern.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/config/riscv/autovec.md diff | blob | blame | history
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