Arm: Fix disassembly error in Thumb-1 relaxed load/store [PR115188]

Arm: Fix disassembly error in Thumb-1 relaxed load/store [PR115188]

A Thumb-1 memory operand allows single-register LDMIA/STMIA. This doesn't get
printed as LDR/STR with writeback in unified syntax, resulting in strange
assembler errors if writeback is selected.  To work around this, use the 'Uw'
constraint that blocks writeback.  Also use a new 'mem_and_no_t1_wback_op'
which is a general memory operand that disallows writeback in Thumb-1.
A few other patterns were using 'm' for Thumb-1 in a similar way, update these
to also use 'mem_and_no_t1_wback_op' and 'Uw'.

gcc:
	PR target/115188
	* config/arm/arm.md (unaligned_loadsi): Use 'Uw' constraint and
	'mem_and_no_t1_wback_op'.
	(unaligned_loadhiu): Likewise.
	(unaligned_storesi): Likewise.
	(unaligned_storehi): Likewise.
	* config/arm/predicates.md (mem_and_no_t1_wback_op): Add new predicate.
	* config/arm/sync.md (arm_atomic_load<mode>): Use 'Uw' constraint.
	(arm_atomic_store<mode>): Likewise.

gcc/testsuite:
	PR target/115188
	* gcc.target/arm/pr115188.c: Add new test.