aarch64: Avoid INS-(W|X)ZR instructions when optimising for speed

aarch64: Avoid INS-(W|X)ZR instructions when optimising for speed

For inserting zero into a vector lane we usually use an instruction like:
	ins     v0.h[2], wzr

This, however, has not-so-great performance on some CPUs.
On Grace, for example it has a latency of 5 and throughput 1.
The alternative sequence:
	movi    v31.8b, #0
	ins     v0.h[2], v31.h[0]
is prefereble bcause the MOVI-0 is often a zero-latency operation that is
eliminated by the CPU frontend and the lane-to-lane INS has a latency of 2 and
throughput of 4.
We can avoid the merging of the two instructions into the aarch64_simd_vec_set_zero<mode>
by disabling that pattern when optimizing for speed.

Thanks to wider benchmarking from Tamar, it makes sense to make this change for
all tunings, so no RTX costs or tuning flags are introduced to control this
in a more fine-grained manner.  They can be easily added in the future if needed
for a particular CPU.

Bootstrapped and tested on aarch64-none-linux-gnu.

Signed-off-by: Kyrylo Tkachov <ktkachov@nvidia.com>
gcc/

	* config/aarch64/aarch64-simd.md (aarch64_simd_vec_set_zero<mode>):
	Enable only when optimizing for size.

gcc/testsuite/

	* gcc.target/aarch64/simd/mf8_data_1.c (test_set_lane4,
	test_setq_lane4): Relax allowed assembly.
	* gcc.target/aarch64/vec-set-zero.c: Use -Os in flags.
	* gcc.target/aarch64/inszero_split_1.c: New test.