RISC-V: Fix overflow check in interleave pattern [PR122970].

RISC-V: Fix overflow check in interleave pattern [PR122970].

In the pattern where we interpret and code-gen two interleaving series as if
they were represented in a larger type we check for overflow.
The overflow check is basically
 if (base + (nelems - 1) * step >> inner_bits != 0)
     overflow = true;

In the PR, base is negative and we interpret it as negative uint64
value.  Thus, e.g. base + (nelems - 1) * step  = -32 + 7 * 8 = 24.
24 fits uint8 and we wrongly assume that no overflow happens.

This patch reinterprets base as type of inner bit size which makes the
overflow check work.

	PR target/122970

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_const_vector_interleaved_stepped_npatterns):
	Reinterpret base as smaller type.

gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Add rvv_zvl128b_ok.
	* gcc.target/riscv/rvv/autovec/pr122970.c: New test.