Fixed a big problem with Cachegrind. I was assuming that any instruction that

Fixed a big problem with Cachegrind.  I was assuming that any instruction that
both read and wrote memory must be doing it to the same address, and was thus
modifying it (eg. 'incl').  But some instructions can read and write different
addresses (eg. pushl %eax, (%ebx)).

Also, it wasn't handling 'rep'-prefixed instructions correctly.  The way they
were instrumented meant that an I-cache access was simulated for every
repetition they do, which is most probably not accurate;  only one I-cache
access should be simulated.

Fixed both of these.  Some largeish changes required, unfortunately:

  - Added 'iddCC' type, the cost-centre for instructions that read and write
    different addresses.   Correspondingly added READ_WRITE_CC as a CC_type.

  - Have to do more correspondingly more complicated things to detect what
    CC_type an x86 instruction is.

  - To handle 'rep' prefixes, now do the I-cache access for such instructions
    before the JIFZ UInstr, so only 1 I-cache access is simulated.  D-cache
    accesses are still done in the same place, so they occur once per
    repetition.

  - Changed the cache simulation log functions;  gone from two to five, we now
    have:

        VG_(log_1I_0D_cache_access)
        VG_(log_0I_1D_cache_access)
        VG_(log_1I_1D_cache_access)
        VG_(log_0I_2D_cache_access)
        VG_(log_1I_2D_cache_access)

    This means fewer spill slots (only 2, I think) have the compact call form,
    which is unfortunate.  Although it's not a problem in the ERASER branch in
    which the helpers aren't hard-wired the way they are in this branch.

Hopefully I've got it right, but I bet I haven't.

git-svn-id: svn://svn.valgrind.org/valgrind/branches/VALGRIND_1_0_BRANCH@856