Bug 495817 - s390x: Fix disassembly for BC[R], BR[C]L, and BIC

Bug 495817 - s390x: Fix disassembly for BC[R], BR[C]L, and BIC

The disassembly of the conditional branch insns bc, bcr, brl, brcl, and
bic differs from objdump's output.  Some examples:

*** mismatch VEX: |bic 20,0|               vs objdump: |bic      0,20|
*** mismatch VEX: |bic 20(%r6),0|          vs objdump: |bic      0,20(%r6)|
*** mismatch VEX: |bic 20(%r4),0|          vs objdump: |bic      0,20(%r4,%r0)|
*** mismatch VEX: |bih 20(%r12)|           vs objdump: |bih      20(%r12,%r0)|
*** mismatch VEX: |nopr|                   vs objdump: |nopr     %r6|
*** mismatch VEX: |b         12(%r11)|     vs objdump: |b        12(%r11,%r0)|
*** mismatch VEX: |blh       12(%r11)|     vs objdump: |blh      12(%r11,%r0)|
*** mismatch VEX: |brc       0,.+0|        vs objdump: |jnop     c|
*** mismatch VEX: |brcl      0,.+0|        vs objdump: |jgnop    c|

All fixed with this patch.

Note that the issue with the base register sometimes being suppressed
affects various other insns as well.