]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Support FP16 for RVV VRGATHEREI16 intrinsic
authorPan Li <pan2.li@intel.com>
Mon, 4 Sep 2023 07:14:28 +0000 (15:14 +0800)
committerPan Li <pan2.li@intel.com>
Mon, 4 Sep 2023 07:45:33 +0000 (15:45 +0800)
commitd99a868a9b100ab5a4b270a1acece60b5b6153a3
treed6d3461ee9f42a5baa34fc875ac3d4985b784ed5
parent1aceceb1e2d6e86ce183c8cc448750fa03b6f79e
RISC-V: Support FP16 for RVV VRGATHEREI16 intrinsic

This patch would like to add FP16 support for the VRGATHEREI16
intrinsic. Aka:

* __riscv_vrgatherei16_vv_f16mf4
* __riscv_vrgatherei16_vv_f16mf4_m

As well as f16mf2 to f16m8 types.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

* config/riscv/riscv-vector-builtins-types.def
(vfloat16mf4_t): Add FP16 intrinsic def.
(vfloat16mf2_t): Ditto.
(vfloat16m1_t): Ditto.
(vfloat16m2_t): Ditto.
(vfloat16m4_t): Ditto.
(vfloat16m8_t): Ditto.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/intrisinc-vrgatherei16.c: New test.
gcc/config/riscv/riscv-vector-builtins-types.def
gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c [new file with mode: 0644]