Tegra TPM driver with HW flow control

Tegra TPM driver with HW flow control

Merge series from Krishna Yarlagadda <kyarlagadda@nvidia.com>:

TPM devices may insert wait state on last clock cycle of ADDR phase.
For SPI controllers that support full-duplex transfers, this can be
detected using software by reading the MISO line. For SPI controllers
that only support half-duplex transfers, such as the Tegra QSPI, it is
not possible to detect the wait signal from software. The QSPI
controller in Tegra234 and Tegra241 implement hardware detection of the
wait signal which can be enabled in the controller for TPM devices.

Add a flag for this in the SPI core and implement support in the Tegra
QuadSPI driver.