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arm: mach-k3: r5: j721e: clk-data: manually set the main_pll3 frequency
authorBryan Brattlof <bb@ti.com>
Wed, 28 Jan 2026 12:36:21 +0000 (18:06 +0530)
committerTom Rini <trini@konsulko.com>
Sat, 7 Feb 2026 21:53:13 +0000 (15:53 -0600)
commitda6d5a93ddac5e60ebc84c75456318fa20a8f995
treecba39663cf250cc9f27b4fa78e95a1eb3c53df70tree
parentc9d1fe757df659338a84c9524c9bfb0545aa1beecommit | diff
arm: mach-k3: r5: j721e: clk-data: manually set the main_pll3 frequency

Moving forward, DM firmware will no longer mess with the MAIN_PLL3.
This means MAIN_PLL3 will need to be manually set to 2GHz in order for
the CPSW9G HSDIV to have the correct 250MHz output for RGMII.

Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
arch/arm/mach-k3/r5/j721e/clk-data.c diff | blob | blame | history
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