RISC-V: Do not use vsetivli for THeadVector.

RISC-V: Do not use vsetivli for THeadVector.

In emit_vlmax_insn_lra we use a vsetivli for an immediate AVL.
XTHeadVector does not support this, so guard appropriately.

	PR target/120461

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Do not emit
	vsetivli for XTHeadVector.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/xtheadvector/pr120461.c: New test.