RISC-V: Add Zicfiss ISA extension.

RISC-V: Add Zicfiss ISA extension.

This patch is implemented according to the RISC-V CFI specification.
It supports the generation of shadow stack instructions in the prologue,
epilogue, non-local gotos, and unwinding.

RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi

gcc/ChangeLog:
	* common/config/riscv/riscv-common.cc: Add ZICFISS ISA string.
	* config/riscv/predicates.md: New predicate x1x5_operand.
	* config/riscv/riscv.cc
	(riscv_expand_prologue): Insert shadow stack instructions.
	(riscv_expand_epilogue): Likewise.
	(riscv_for_each_saved_reg): Assign t0 or ra register for
	sspopchk instruction.
	(need_shadow_stack_push_pop_p): New function. Omit shadow
	stack operation on leaf function.
	* config/riscv/riscv.h
	(need_shadow_stack_push_pop_p): Define.
	* config/riscv/riscv.md: Add shadow stack patterns.
	(save_stack_nonlocal): Add shadow stack instructions for setjump.
	(restore_stack_nonlocal): Add shadow stack instructions for longjump.
	* config/riscv/riscv.opt (TARGET_ZICFISS): Define.

libgcc/ChangeLog:
	* config/riscv/linux-unwind.h: Include shadow-stack-unwind.h.
	* config/riscv/shadow-stack-unwind.h
	(_Unwind_Frames_Extra): Define.
	(_Unwind_Frames_Increment): Define.

gcc/testsuite/ChangeLog:
	* gcc.target/riscv/ssp-1.c: New test.
	* gcc.target/riscv/ssp-2.c: New test.

	Co-Developed-by: Greg McGary <gkm@rivosinc.com>,
			Kito Cheng <kito.cheng@gmail.com>